Working of the Programmable Interrupt Controller (in a hypothetical use case)

I'm doing a bit of OSdev, and I'm doing interrupt handling now.

I have a few questions regarding the working of the PIC.

Let's assume that we have one PIC. This would have 8 input lines (IRQs /IRs - which is the correct terminology??). It should also have an output to the processor (INTR along with an INTA for request and acknowledgement). Moreover it must also have data lines for communication with the processor and that seems to be it for this scenario. Inside, it must have the In-service-register, Interrupt-request-register and the interrupt-mask-register.

I'm guessing that all of these are 8 bits in size.

Suppose we start off with the PIC in edge triggered operation mode. I'm guessing all the registers will have a value 0 (all bits 0). Is this right?

Now an external device sends a pulse (a short trigger) along IRQ0. I'm guessing that the IRR becomes 0b00000001 now?. What does the PIC do now?

Here's my guess - It checks the IMR, which is 0b00000000. It realizes that the interrupt isn't masked and sets the ISR to 0x00000001 and interrupts the processor (intr line). **What happens to the IMR here? What's its state? I know that other interrupts are masked or something... So is IMR = 0b11111111?? **

So continuing with the scenario, the processor sends inta, to which the PIC sends the vector number of the interrupt to the processor,(which is nothing but the IRQ + the vector offset that was programmed into the PIC initially) and the processor does it's thing, i.e, push the EFLAGS,CS,EIP registers on the stack and jump to the interrupt routine, and so on.

Now the processor is working on the interrupt and hasn't sent the EOI command to the PIC yet.

What happens when some other interrupt (eg. IRQ1) fires now? What will be the state of the PIC registers?

What would happen after the processor issues the EOI command to the PIC??