This is scanning code
uint32_t pci_read_configd(uint8_t bus, uint8_t dev, uint8_t func, uint8_t offset)
{
uint32_t address;
uint32_t lbus = (uint32_t)bus;
uint32_t ldev = (uint32_t)dev;
uint32_t lfunc = (uint32_t)func;
address = (uint32_t)((lbus << 16) | (ldev << 11) | (lfunc << 8) | (offset & 0xfc) | ((uint32_t)1 << 31));
out_port32(0xcf8, address);
return in_port32(0xcfc);
}
void init_pci(void)
{
klog("pci","scanning device...");
for (size_t i = 0; i < 16; i++)
{
for (size_t l = 0; l < 128; l++)
{
if(pci_read_configd(i,l,0,0) != 0xffff)
{
klog("pci","found device at Bus.%h Dev.%h ID:%h BAR1:%h",i,l,pci_read_configd(i,l,0,0));
}
}
}
for (size_t i = 0; i < 0x3c; i+=4)
{
klog("pci","%h at %h" ,pci_read_configd(0,3,0,i),i);
}
klog("pci","OK");
}
this is the real pci device info (by qemu monitor)
(qemu) info pci
Bus 0, device 0, function 0:
Host bridge: PCI device 8086:1237
id ""
Bus 0, device 1, function 0:
ISA bridge: PCI device 8086:7000
id ""
Bus 0, device 1, function 1:
IDE controller: PCI device 8086:7010
BAR4: I/O at 0xc040 [0xc04f].
id ""
Bus 0, device 1, function 3:
Bridge: PCI device 8086:7113
IRQ 9.
id ""
Bus 0, device 2, function 0:
VGA controller: PCI device 1234:1111
BAR0: 32 bit prefetchable memory at 0xfd000000 [0xfdffffff].
BAR2: 32 bit memory at 0xfebf0000 [0xfebf0fff].
BAR6: 32 bit memory at 0xffffffffffffffff [0x0000fffe].
id ""
Bus 0, device 3, function 0:
Ethernet controller: PCI device 8086:100e
IRQ 11.
BAR0: 32 bit memory at 0xfebc0000 [0xfebdffff].
BAR1: I/O at 0xc000 [0xc03f].
BAR6: 32 bit memory at 0xffffffffffffffff [0x0003fffe].
id ""
This is the result of PCI bus0 dev3 func0 manual scanning
[0x00000000]pci:scanning device...
[0x00000000]pci:found device at Bus.0x00000000Dev.0x00000000
[0x00000000]pci:found device at Bus.0x00000000Dev.0x00000001
[0x00000000]pci:found device at Bus.0x00000000Dev.0x00000002
[0x00000000]pci:found device at Bus.0x00000000Dev.0x00000003
[0x00000000]pci:0x00008086at 0x00000000
[0x00000000]pci:0x00000103at 0x00000004
[0x00000000]pci:0x00000003at 0x00000008
[0x00000000]pci:0x00000000at 0x0000000C
[0x00000000]pci:0x00000000at 0x00000010
[0x00000000]pci:0x0000C001at 0x00000014
[0x00000000]pci:0x00000000at 0x00000018
[0x00000000]pci:0x00000000at 0x0000001C
[0x00000000]pci:0x00000000at 0x00000020
[0x00000000]pci:0x00000000at 0x00000024
[0x00000000]pci:0x00000000at 0x00000028
[0x00000000]pci:0x00001AF4at 0x0000002C
[0x00000000]pci:0x00000000at 0x00000030
[0x00000000]pci:0x00000000at 0x00000034
[0x00000000]pci:0x00000000at 0x00000038
[0x00000000]pci:OK
out_port32 is an encapsulation of outl instructions in_port32 is the same
I found one thing, every time I read in, I can only read one WORD(is it helpful?)
But according to the PCI standard, there is no problem with such code implementation
I also used the sample code of OSDEV Wiki The problem still exists https://wiki.osdev.org/PCI
If you have any questions about other codes, you can visit github: LithiumOS-Team Lithium-OS
Thank you for your any help
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