RISC-V Load address not aligned to word boundary

My compiler is RARS.

Here is the problem. I was told that I need to define a memory base address, and the use of pseudoinstructions is not allowed. So, I cannot use la, li, and j

When I tried to do it, I got this error:

Error in /Users/SumOfArray.asm line 22: Runtime exception at 0x00400018: Load address not aligned to word boundary 0x00000001

Go: execution terminated with errors

Line 22 that I think have the mistake is this one: lw t4,0(t3) After creating lui instruction. I will need to loop through it to save values into an array.

I guess I am asking how can I fix my code below, to have a lui instruction and loop through the array with no errors.

  .data
array:      .word 1,2,3,4,5,6,7,8,9,10,11,12,-1,-2,-3,-4,-5,-6,-7,-8,-9,-10,-11,-12,-5, 0 
positiveSum:    .word 0
negativeSum:    .word 0

   .text

main:
    lui s0, 0x10010
        lw t0,0(s0)      #load array to register t0 
        lw s1,0(s0)      #load the positive sum to s1, and negative sum to s2           
        lw s2,0(s0)

loop:                   #store values in an array using loop
    slli t3,t1,2
    add t3,t3,t0        #add the base address and the above result
    lw t4,0(t3)         #load the word from above address into t4
    beqz t4,exit        #exit loop when reaching 0

The problem you are having is that you are trying to use lw with the address (t1 << 2) + t0. T0 is equal to 1 on first use (unless it has been modified in the meantime) which gives an unaligned word address. Not being supported (or at least not by default) this gives the error you saw.

May be misaligned access are disabled by default. There what the specification tell:

For best performance, the effective address for all loads and stores should be naturally aligned for each data type (i.e., on a four-byte boundary for 32-bit accesses, and a two-byte boundary for16-bit accesses). The base ISA supports misaligned accesses, but these might run extremely slowly depending on the implementation. Furthermore, naturally aligned loads and stores are guaranteed to execute atomically, whereas misaligned loads and stores might not, and hence require additional synchronization to ensure atomicity.

To avoid the error you are facing there is two possibilities:
You really need to do misaligned access and you have to enable this feature.
What you want is read the first word , second ... then what you need to do is to shift the elements you get from the array ( by 2 to the left).

lw s1,0(s0)      #load the positive sum to s1, and negative sum to s2           
lw s2,0(s0)

need to be replaced probably by :

lw t4,0(t3)     
sw s1, 0(s0)    
sw s2, 4(s0)    

also:

lui s0, 0x10010
    lw t0,0(s0)   #load array to register t0 
    lw s1,0(s0)   #load the positive sum to s1, and negative sum to s2           
    lw s2,0(s0)

needs to be replaced by:

main:
    la t0, array
    la s0, positiveSum