STM32H7 QSPI BUSY bit Never Gets Cleared

I am using an STM32H750 MCU and I'm trying to test the QSPI peripheral. Here is my code so far:

    QUADSPI->CR     = 0x3100048     // QUADSPI_CR: PRESCALER=3, APMS=0, FTHRES=0, FSEL=0, DFM=1, SSHIFT=0, TCEN=1
    QUADSPI->DCR    = 0x001A0200    // QUADSPI_DCR: FSIZE=0x1A, CSHT=0x02, CKMODE=0
    QUADSPI->LPTR   = 0x00001000    // QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
    QUADSPI->CR     = QUADSPI_CR | 0x01 // Enable QSPI peripheral

    while(QUADSPI->SR & 0x20) {}    // Wait for BUSY bit to be cleared.

    QUADSPI->CCR    = 0x00000106    // QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable

    while(QUADSPI->SR & 0x20) {}    // Wait for BUSY bit to be cleared.

    QUADSPI->DLR    = 0x01          // QUADSPI_DLR: 2 bytes
    QUADSPI->CCR    = 0x01000181    // QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Volatile Conf. Reg.
    
    while(!QUADSPI->SR & 0x04) {}   // Wait for FTF flag to be set.

    QUADSPI->DR     = 0xABAB    // QUADSPI_DR: Load 0xABAB into FIFO.

    while(QUADSPI->SR & 0x20) {}    // Wait for BUSY bit to be cleared.

The problem I am running into is that after I execute this line:

QUADSPI->CCR = 0x00000106

I wait for the BUSY bit in the status register to get cleared and it never does, it just reports back with 0x24. I confirmed that the BUSY bit is cleared before I write to the CCR register, if it wasn't then it would get stuck in the while loop that precedes the write to the CCR register. I can see the instruction sent out across the QSPI bus (0x06). The bus transaction looks fine, but for some reason the BUSY bit just never gets cleared.

Can anyone with experience on this MCU see anything wrong with my implementation?

Thank you.