Usage of delay in clock enabling GPIO

I am currently just beginning to work on an ARM Cortex-M4 MCU and i came across this code in initialising of a I/O port.

SYSCTL_RCGC2_R |= 0x00000020;     // 1) activate clock for Port F
delay = SYSCTL_RCGC2_R;           // allow time for clock to start
GPIO_PORTF_LOCK_R = 0x4C4F434B;   // 2) unlock GPIO Port F
GPIO_PORTF_CR_R = 0x1F;           // allow changes to PF4-0
....

i do not get the second line of code. What does assigning SYSCTL_RCGC2_R to delay do? How does that "allow time for clock to start"

What does assigning SYSCTL_RCGC2_R to delay do?

It is literally a specific delay and only uses a single instruction (when optimized).

Rember that Cortex-M4 has a write buffer - that means the clock register write won't go into effect when the next instruction(s) execute.

Because peripherial memory is strongly ordered, the following dummy read has to wait for the write operation to finish first, and only then actually read the value. That is also the point in time when the GPIO clock activates and can be accessed.

You often see this pattern when peripherials run on a slower clock than the main MCU core.