Clearing the Hardfault or Usage faults in Cortex-M4 processor


While working on implementation of system faults for the system with ARM cortex-m4 microprocessor. I have enabled usage faults using System Handler Control and State Register,


and enabled divide by zero faults using configurable control register.


I'm also trying to avoid entering into usage fault multiple times, I want the program to hit usage fault ISR only once whenever a fault has occurred, but instead, the program hits the usage fault multiple times. I tried to use NVIC_ClearPendingIRQ(IRQnum) but did not resolve the issue.

Can someone help me if I'm missing to set any register or some thing?

Code for ISR:

void UsageFault_Handler(void)
//  CFSR (Configurable Fault status register)
//  |--------------------|----------|---------|  UFSR - usage fault status register.
//  |        UFSR        |   BFSR   |   MFSR  |  BFSR - bus fault status register.
//  |--------------------|----------|---------|  MFSR - MemManage Fault status register. 
//  31                16   15      8  7      0
// ensure the USFR register is not empty before checking for particular usage faults. 
  if ((SCB->CFSR & 0xFFFF0000) != 0)
    uint32_t CFSRValue = SCB->CFSR;// get the CFSR register and shift the register to extract the UFSR bits.
    CFSRValue >>= 16;                                                 // right shift to lsb

     if ((CFSRValue & (1 << 9)) != 0) // ensure the 25th bit (DIVBYZERO) of CFSR is not set. 
       LOG the fault

I'm using IAR with ucos-III for ARM cortex-m4.

asked on Stack Overflow Mar 13, 2020 by krishna • edited Mar 13, 2020 by Ðаn

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