Question about design CPU base on RISC-V architecture

My school project is design a CPU base on RISC-V via verilog, I complete the instrucrtion's table but when I use rars1_4 for simulate an example assembly code, I can compile it. But when I start to run to see how the Instruction run, this program says: "Error in D:\CauTrucMayTinh\RISC-V\RISCV_project\factorial.asm line 1: Runtime exception at 0x00400000: address out of range 0x00000028

Step: execution terminated with errors." I try to search on Google but I can't find any reply relate my problem. This is my code:

lw  a0,40(zero)
addi    a1,zero,1
addi    a2,zero,1
beq a0,a1,SAVE
LOOP:
addi    a1,a1,1
addi    t1,a1,0
addi    t2,a2,0
jal ra,MUL
add a2,zero,t0
bne a1,a0,LOOP
SAVE:
sw  a2,44(zero)
jal x0,DONE
MUL:
andi    t0,t0,0
LOOP_MUL:
add t0,t0,t2
addi    t1,t1,-1
bne t1,zero,LOOP_MUL
jalr    zero,ra,0
DONE:
add zero,zero,zero

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