LDRD hard faulting during execution

I'm creating a polymorphic-code and I have an issue with the LDRD instruction that is making me crazy, I cannot see it. NMI hardfault at execution obviously. I'm on a STM32L4A6AG. Problem probably resides in assembly code but could maybe also be on opcode generation (Ignored by disassembler?).

Data is taken before ldrd execution:

My code:

2004ffc0: 0xbff36f8f   isb     sy
2004ffc4: 0xbff34f8f   dsb     sy
2004ffc8: 0x000020b5   push    {r5, lr}
2004ffca: 0xdff80c50   ldr.w   r5, [pc, #12]   ; 0x2004ffd8
2004ffce: 0xdfe90301   ldrd    r0, r1, [pc, #12]       ; 0x2004ffdc
2004ffd2: 0x0000a847   blx     r5
2004ffd4: 0x000000bf   nop     
2004ffd6: 0x000020bd   pop     {r5, pc}

Registers:

    r0  0x0 (Hex)   
    r1  0x1 (Hex)   
    r2  0x2004ffc0 (Hex)    
    r3  0x2004ffbf (Hex)    
    r4  0xaabbccdd (Hex)    
    r5  0x80107e1 (Hex) 
    r6  0x0 (Hex)   
    r7  0x2004ff98 (Hex)    
    r8  0   
    r9  0   
    r10 0   
    r11 0   
    r12 0   
    sp  0x2004ff90  
    lr  0x80104ed (Hex) 
    pc  0x2004ffce  

Memory:

x/9wx 0x2004ffc0
0x2004ffc0: 0x8f6ff3bf  0x8f4ff3bf  0xf8dfb520  0xe9df500c
0x2004ffd0: 0x47a80103  0xbd20bf00  0x080107e1  0xeeffaabb
0x2004ffe0: 0xaabbccdd

x/18hx 0x2004ffc0
0x2004ffc0: 0xf3bf  0x8f6f  0xf3bf  0x8f4f  0xb520  0xf8df  0x500c  0xe9df
0x2004ffd0: 0x0103  0x47a8  0xbf00  0xbd20  0x07e1  0x0801  0xaabb  0xeeff
0x2004ffe0: 0xccdd  0xaabb

Thanks guys!

According to the ARM manual, ldrd instructions with a pc-relative addressing mode must be be word-aligned on ARMv7-M parts. If the assembler does not take care of this quirk, manual alignment may be needed:

.align
ldrd r0, r1, [pc, #12]