RISC-V SiFive HiFive Unleashed FMSUB.S(32) underflow flag behaves differently depending on rounding

1

Here's the situation. I am executing instruction FMSUB.S on mentioned in the title hardware. I am using operands values as such: 0xB3800000*0x00500000-0x80800000, with rounding to nearest-even. If I am correct GRS after this operation will be 0x5, therefore rounding happens and final result is a normal value of 0x00800000, but underflow flag is being set. Second try but this time with rounding towards +infinity(up). The same operation, the same result, however underflow flag this time is not being set. Inexact flag in both cases is being set. The same operation made with rounding to nearest-ties to max magnitude behaves the same way as nearest-even. Rounding -infinity with operands 0x33800000*0x00500000-0x00800000(changing signs basically) acts the same as +infinity with previous operands.

My question is, where does that difference in underflow flag come from ?

assembly
floating-point
cpu-architecture
ieee-754
riscv
asked on Stack Overflow Oct 25, 2019 by Mateusz Kowalski • edited Oct 31, 2019 by Mateusz Kowalski

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