EDIT: exhuming this question since I'm back on the issue. I've added some source code and details.
I try to record the execution trace of my firmware running on STM32H753. For this I'm using the ETM functionality of Cortex M7. I don't want to use external tools but rather use the ETF (Embedded Trace FIFO) that can be accessed directly from the processor.
I have been struggling to understand how the different debug components (ETM, ETF, DWT, etc...) are working together.
My understanding is that DWT peripheral compares the execution address and triggers the ETM if it matches. Then the ETM feeds the ETF (?).
Here is the code:
// enable DWT in Debug Exception and Monitor Control Register
*DEMCR |= 1<<24; // trace enable
// Generates CMPMATCH event: from Archiecture Ref Manual of ARM v7 -> "the CMPMATCH[N] signals
// from the DWT unit are available as control inputs to the ETM unit"
*DWT_COMP0 = 0x00000000; // adress comparator
*DWT_MASK0 = 24;
*DWT_FUNCT0 = 0x00000008; // generate CMPMATCH[0] event
// setup ETM
*ETM_LAR = 0xC5ACCE55; // unlock periph
*ETM_CONFIG = (*ETM_CONFIG) | 0x00031F30; // enable all traces
*ETM_PRGCTRL = 1; // enable ETM
// setup ETF (by default in circular mode)
*ETF_LAR = 0xC5ACCE55; // unlock periph
*ETF_FFCR = 0x00001123; // ARM recommends to set bits TRIGONTRIGIN FONTRIGEVT STOPONFL ENTI AND ENFT
*ETF_TRG = 16; // number of 32 words to capture
*ETF_CTL = 1; // enable trace
// bullshit processing just to fill the trace
U4_INDEX = 1000;
while(U4_INDEX--)
__asm("nop");
// wait for bit READY
while ( ((*ETF_STS) & (1<<2)) == 0 );
// read trace
printf("*ETF_RRD=0x%x\r\n", *ETF_RRD);
printf("*ETF_RRD=0x%x\r\n", *ETF_RRD);
printf("*ETF_RRD=0x%x\r\n", *ETF_RRD);
printf("*ETF_RRD=0x%x\r\n", *ETF_RRD);
*ETF_CTL = 0; // disable trace
The READY bit of ETF_STS is never rising.
My question is: how to setup the different debug components to launch the trace execution (to record instructions) ?
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