Why fill “0x50C06” to level 1 page table entry?

Why fill the table entry with value 0x50C06 in the follow code?

    TTB_ENTRY_SUPERSEC_DEV  DEFINE   0x50C06 
                                           ; Setup page table.
    LDR     r0,=SFE(MMU_TT)                     ; Load page table base address


                                                ; Init the whole page table as dev memory by default
    MOV     r4, #0x00000000
    MOV     r3, r0
    ADD     r3, r3, #0x0

TTbl_Dev_Loop1
    MOV32   r1, #TTB_ENTRY_SUPERSEC_DEV
    ADD     r1, r1, r4
    MOV     r5, #16
TTbl_Dev_Loop2
    STR     r1, [r3], #4
    SUBS    r5, r5, #1
    BNE     TTbl_Dev_Loop2
    ADD     r4, r4, #0x1000000
    CMP     r4, #0x0
    BNE     TTbl_Dev_Loop1

The first level ARM page table has sections and super sections.

Bits    |31   24|  20|19|18|17|16| 15|14 12|11 10|9|8    5| 4|3|2|1|0
--------+------------+--+--+--+--+---+-----+-----+-+------+--+-+-+-+-
Section |Base address|NS| 0|nG| s|APX|  TEX|   AP|P|Domain|XN|C|B|1|0
Super   |Base   | SBZ|NS| 1|nG| s|APX|  TEX|   AP|P|Ignore|XN|C|B|1|0
0x50C06 |            | 0| 1| 0| 1|0  |  000|   11|0|  0000| 0|0|1|1|0
is super|            |  | *|...

These allow mapping a large portion of memory 16MB at a time. Each first level table entry represents 1MB of address space. Super sections repeats this 16 times for a total of 16MB. This is the code,

    MOV     r5, #16         ; 16 entries.
TTbl_Dev_Loop2
    STR     r1, [r3], #4    ; write entry
    SUBS    r5, r5, #1      ; decrement and test for zero.
    BNE     TTbl_Dev_Loop2  ; branch if more needed.

The rest of the code just changes the base with the r4 register. ADD r4, r4, #0x1000000 is stepping 16MB through the address space. So this maps all virtual addresses to the physical addresses. This is often used during booting a system, when the MMU is first turned on and cache can be enabled. Typical devices don't have 4GB of actual physical memory (and peripherals), so the unused physical addresses can be re-used by updating the table. It is also possible to change the super sections to have page table entries (l2 page tables with 4-64Kb sizes) as the system is running.

It also seems that all the memory is set to device memory (at least to start) so that no type of caching will be used. Some of these other bits (AP,TEX,etc) depend on CP15 register values which are not shown.

See also: ARMv7 One-to-One mapping
                Change TTB_BASE
                ARM Paging