What's the closet data type in VHDL to the classic c-language data type "uint32_t", example:
#include "stdint.h"
void main() {
uint32_t data = 0xFFFFFFFF;
}
From my understanding, VHDL's "positive" and "natural" types are just subsets of a signed "integer" type and are missing half of the range of c-langauge uint32_t type.
architecture sim of testbench is
--integer range: -2,147,483,648 to +2,147,483,647
--same as c-language int32_t
signal a0 :integer := 1;
--integer range: 0 to +2,147,483,647
--same as c-language int32_t and'ed with 0x7FFFFFFF
signal a1 :natural := 1;
--integer range: 1 to +2,147,483,647
--same as c-language int32_t and'ed with 0x7FFFFFFF, and 0 thrown away
signal a2 :positive := 1;
--integer range: -1 to -2,147,483,648
--same as c-language int32_t or'ed with 0x80000000, and 0 thrown away
signal a3 :negative := 1;
--unsigned integer range: 0 to 4,294,967,295
--?????? does it exist in VHDL?
signal a4 :uint32_t
begin
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testit is
end entity;
architecture sim of testit is
subtype uint32_t is unsigned(31 downto 0);
signal a1 :uint32_t := X"FFFFFFFF";
signal a2 :uint32_t := X"AFFFFFFF";
-- Error out of bounds
--signal a3 :integer := 16#FFFFFFFF;
begin
end architecture;
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