Vivado/XSDK: How to access address from Zynq M_AXI_GP0 Bus?


Let's say I built a vivado Zynq FPGA project, and I want to write and read the Zynq's "M_AXI_GP0" port from a c-program running on the zynq as follows. Further, let's suppose the address I want to read and write on the "M_AXI_GP0" port of the Zynq is address "0x000A1000". How would I do that in the code below? Do I need to worry about virtual address to physical address translation in the ARM? is there a XIL api for that? etc... see code example:

#include <stdio.h>
#include "platform.h"

#include "xil_printf.h"

void write(uint32_t addr, uint32_t wdata) {
   //????? how to implement

uint32_t read(uint32_t addr) {
    return 0;

int main()

    print("Hello World\n\r");

    uint32_t beef;
    write(0x000A1000, 0xDEADBEEF);
    write(0x000A1004, 0x12345678);
    beef = read(0x000A1000);

    return 0;

Xilinx ZYNQ - ARM CORTEX A9 -Xilinx SDK

asked on Stack Overflow Jun 11, 2019 by pico • edited Jun 11, 2019 by pico

2 Answers


The "xil_ io.h" file contains the interface for the general IO component, which encapsulates the Input/Output functions for processors that do not require any special I/O handling:

u32  Xil_In32  (UINTPTR Addr);
void Xil_Out32 (UINTPTR Addr, u32 Value);

The "M_AXI_GP0" Bus is mapped to the PL or "Programmable Logic" address region in the Zynq Address Map:

Xilinx Zynq: ARM Cortex A9 Memory Map

DDR                    0x00000000 - 0x3FFFFFFF
PL                     0x40000000 - 0xBFFFFFFF
Reserved               0xC0000000 - 0xDFFFFFFF
Memory mapped devices  0xE0000000 - 0xE02FFFFF
Reserved               0xE0300000 - 0xE0FFFFFF
NAND, NOR              0xE1000000 - 0xE3FFFFFF
SRAM                   0xE4000000 - 0xE5FFFFFF
Reserved               0xE6000000 - 0xF7FFFFFF
AMBA APB Peripherals   0xF8000000 - 0xF8FFFFFF
Reserved               0xF9000000 - 0xFBFFFFFF
Linear QSPI - XIP      0xFC000000 - 0xFDFFFFFF
Reserved               0xFE000000 - 0xFFEFFFFF
OCM                    0xFFF00000 - 0xFFFFFFFF
answered on Stack Overflow Jun 12, 2019 by pico

Did you see the AXI GPIO driver and example in here? Whether you need to worry about virtual to physical address translation depends on what exactly are you running? Do you have a bare metal/RTOS setup?

answered on Stack Overflow Jun 12, 2019 by Sanchayan Maity

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