Zynq + Microblaze share DDR memory address map inconsistent in SDK

I have a block design with a Zynq and Microblaze on an Xilinx Zed board.

I want the microblaze to be able to access DDR memory shared with the arm corers in the PS. My microblaze uses a cache. There are two AXI ports on the microblaze M_AXI_DC, M_AXI_IC that need to be connected so that they have access to the PS DDR memory.

The DDR memory of the PS is accessible via two separate smart interconnects:

     mb M_AXI_DC <-smart interconnect 1-> S_AXI_HP0 zynq 

     mb M_AXI_IC <-smart interconnect 2-> S_AXI_HP1 zynq

The address editor shows the following address map

This design synthesizes without errors. When I export this design to the SDK the hdf file shows another memory layout:

1. Why the difference?

The PS address map in the hdf file shows that the DDR memory starts at 0x0010_0000

Lets assume that the DDR is address map for the microblaze had the DDR memory at an offset address of 0x2000_0000. Does this mean that if I want to address DDR memory at 0x00000001:

2. On the microblaze I write to 0x2000_0001
3. On the zynq I write to 0x0010_0001