How to flush cache line in aarch64

How can I flush the cache line on aarch64 inside the userspace code? Just like on x86 we can use the following lib call:

_mm_clflush(&array);

I tried the following code:

void flush(void)
{
    asm volatile ( "MCR p15, 0, =0x0,c7, c6, 0\n");
    return;
}

But GCC has compiling error:

Error: unknown mnemonic `mcr' -- `mcr p15,0,=0x0,c7,c6,0'

Thanks.

Update from @Peter's comment: I tried the __builtin___clear_cache with the following code:

int tt = 0;
unsigned long *ptr;

tt++;
TIMESTAMP(ts2);
printf("cycle: %lu. %d\n", ts2-ts1, tt);

ptr = &tt;
__builtin___clear_cache(ptr, ptr+128);
TIMESTAMP(ts1);
tt++;
TIMESTAMP(ts2);
printf("cycle: %lu. %d\n", ts2-ts1, tt);

The result seems doesn't show we have successfully evicted the data out of the data cache:

cycle: 5. 1
cycle: 0. 2

I looked at the disassembly, and referenced the AARCH64 instruction manual. It seems that the builtin function has clean the cache, right?

0000000000400788 <__clear_cache>:
  400788:       14000002        b       400790 <__aarch64_sync_cache_range>
  40078c:       00000000        .inst   0x00000000 ; undefined

0000000000400790 <__aarch64_sync_cache_range>:
  400790:       b0000083        adrp    x3, 411000 <_GLOBAL_OFFSET_TABLE_+0x28>
  400794:       b9404462        ldr     w2, [x3,#68]
  400798:       35000082        cbnz    w2, 4007a8 <__aarch64_sync_cache_range+0x18>
  40079c:       d53b0024        mrs     x4, ctr_el0
  4007a0:       2a0403e2        mov     w2, w4
  4007a4:       b9004464        str     w4, [x3,#68]
  4007a8:       d3504c44        ubfx    x4, x2, #16, #4
  4007ac:       52800083        mov     w3, #0x4                        // #4
  4007b0:       12000c45        and     w5, w2, #0xf
  4007b4:       1ac42064        lsl     w4, w3, w4
  4007b8:       51000482        sub     w2, w4, #0x1
  4007bc:       1ac52063        lsl     w3, w3, w5
  4007c0:       8a220002        bic     x2, x0, x2
  4007c4:       93407c84        sxtw    x4, w4
  4007c8:       eb01005f        cmp     x2, x1
  4007cc:       540000a2        b.cs    4007e0 <__aarch64_sync_cache_range+0x50>
  4007d0:       d50b7b22        dc      cvau, x2
  4007d4:       8b040042        add     x2, x2, x4
  4007d8:       eb02003f        cmp     x1, x2
  4007dc:       54ffffa8        b.hi    4007d0 <__aarch64_sync_cache_range+0x40>
  4007e0:       d5033b9f        dsb     ish
  4007e4:       51000462        sub     w2, w3, #0x1
  4007e8:       93407c63        sxtw    x3, w3
  4007ec:       8a220000        bic     x0, x0, x2
  4007f0:       eb00003f        cmp     x1, x0
  4007f4:       540000a9        b.ls    400808 <__aarch64_sync_cache_range+0x78>
  4007f8:       d50b7520        ic      ivau, x0
  4007fc:       8b030000        add     x0, x0, x3
  400800:       eb00003f        cmp     x1, x0
  400804:       54ffffa8        b.hi    4007f8 <__aarch64_sync_cache_range+0x68>
  400808:       d5033b9f        dsb     ish
  40080c:       d5033fdf        isb
  400810:       d65f03c0        ret
  400814:       00000000        .inst   0x00000000 ; undefined

1. "MCR p15, 0, =0x0,c7, c6, 0\n" is Aarch32 instruction

2. As @Peter mentioned above 'flush' (or 'clean' in ARM TRM terms) copies data from cache into a memory but cache copy is still valid. Simply speaking, your __builtin___clear_cache test is a mess.

3. 'Invalidate' remove data from a cache and ensure data are read out of memory. (There is a catch though, after invalidating data could be prefetched back into a cache. So even with invalidation your test might be a mess).

4. Check ARM TRM for 'Clean by VA' instructions, most/all of them could be executed out of user-space. Be aware that access could be disabled/trapped by an operation system, in that case your app would generate a fault and likely would be terminated by OS.

PS: What you trying to archive by that flushing, btw?