Shared DDR memory between rocket and ARM A9 processors running bare-metal application on Zedboard

I'm running a bare-metal application on rocket chip processor from lowrisc repository on Zedboar* (link).

In that configuration, the external memory is the DDR. Also, a bare-metal application runs on the ARM A9 (with caches disabled) from the PS of zynq. The DDR is shared between both ARM and rocket.

The default rocket address for external memory on rocket lowrisc is 0x80000000, and then this address is converted to 0x10000000 at the wrapper.v to use the DDR from zedboard.

My goal is to write the rocket application results in the DDR and the arm app to access them.

However, I'm not able to do that. The rocket app runs successfully, but doesn't write the DDR memory, even the address being hard defined, for instance:

volatile uint32_t *a = (volatile uint32_t *)0x80000000;
*a = 5;

My guess the data is stored on the rocket caches and not written on DDR. The rocket caches cannot be disabled, can it? And, I didn't find any command to flush the caches.

In this page it is described that all memory write is buffered and the actual update to the memory map is triggered by a write to 'mem_update'. However, I could not write 'mem_update' in the bare-metal app.

I just want to make an IO communication. Is there any straightforward way?

Thank you in advance.