Indeterminate register values in hdl simulation

I am trying to simulate an AXI4(Full) master using Vivado. It is supposed to write the following values on the slave side(which, in my case, is gonna be some registers in my zedboard PS)

0x0000fe01 to 0xe000a204
0x0000fe01 to 0xe000a208
0x00000001 to 0xe000a040

I checked the AXI protocol and this the FSM that I have to implement.

Here is the block level design.

When I run behavioural synthesis, It works.

However when I try to run post synthesis functional simulation (Which is supposedly closer to the actual design and includes gate delays), I am getting some indeterminate values

Here is the complete project and the master IP if you need to check it.

vivado project(using vivado 2015.2) axi_controller

Here are the individual verilog files(just for ease of access) in the top down order:

axi_controller_testbench.v

design_1_wrapper.v

design_1.v

axi_controller_v1_1.v(This is where I make the state calculation for the FSM I send the state to the interface unit so it can assign proper values to the ports)

axi_controller_v1_1_M00_AXI.v(This is the interface unit in the IP)

I have narrowed the problem down to this part in my code.

//state updation
always @(posedge m00_axi_aclk) begin
    if(m00_axi_aresetn==1'b0) begin
        cur<=t_0;
        next<=t_0;
    end
    else begin
        cur<=next;
    end
end

//state calculation
always @(*) begin
    case(cur) 
        t_0: begin
            if(m00_axi_init_axi_txn) next=t_1;
            else next=t_0;
        end
        t_1: begin
            next=t_2;
        end
        t_2: begin
            if(m00_axi_awready) begin
                if(m00_axi_wready) next=t_4;
                else next=t_3;
            end
            else next=t_2;
        end
        t_3: begin
            if(m00_axi_wready) next=t_4;
            else next=t_3;
        end
        t_4: begin
            if(m00_axi_awready) begin
                if(m00_axi_wready) next=t_6;
                else next=t_5;
            end
            else next=t_4;
        end
        t_5:  begin
            if(m00_axi_wready) next=t_6;
            else next=t_5;
        end
        t_6: begin
            next=t_6;
        end
    default next=t_0;
    endcase
end

where,

parameter t_0=3'b000, 
parameter t_1=3'b001, 
parameter t_2=3'b010,
parameter t_3=3'b011, 
parameter t_4=3'b100, 
parameter t_5=3'b101, 
parameter t_6=3'b110,

At 100ns when INIT_AXI_TRANS changes from 0 to 1 next becomes 00x

since cur is 000 (or t_0) the first case should be implemented. As next becomes 00x, I think it's unable to find whether INIT_AXI_TRANS is 0 or 1. This effect is then propagating through the rest of the circuit.

Can anyone please help me find out how i can fix this.
Thanks in advance.

---

I did what was suggested in the first comment, and have updated the code here and in the git repository. Sadly, it seems that was not the problem as I am still getting the same result.

You are assigning a value to next in multiple processes. In the reset process and in state change process.