I'm trying to understand this examble about LDM and STM instructions, but I have a problem with the final result, here is the example:
PRE
r0 = 0x00009000
r1 = 0x00000009
r2 = 0x00000008
r3 = 0x00000007
STMIB r0!, {r1 - r3}
MOV r1, #1
MOV r2, #2
MOV r3, #3
PRE(2)
r0 = 0x0000900C
r1 = 0x00000001
r2 = 0x00000002
r3 = 0x00000003
LDMDA r0!, {r1 - r3}
POST
r0 = 0x00009000
r1 = 0x00000009
r2 = 0x00000008
r3 = 0x00000007
I have do this and I obtain that:
r0 = 0x00009000
r1 = 0x00000007
r2 = 0x00000008
r3 = 0x00000009
I don't know where I'm wrong, the only possibility I can think is about that STM instruction starts in R3 and not at R1
how it is actually implemented is in the source code which most folks dont have access to and there is no reason to assume that from core/implementation to another it does it the same way. despite the pseudo code they might walk the register list top to bottom instead of bottom to top or have a look up table, etc. They might do an 8 or 4 word store that they prepped up rather than wasting a ton of cycles doing 1 word at a time. How they actually do it in the logic is not important, or shouldnt be for understanding. How it ends up in memory is.
stmib increment before
start_address = Rn + 4
end_address = Rn + (Number_Of_Set_Bits_In(register_list) * 4)
if ConditionPassed(cond) and W == 1 then
Rn = Rn + (Number_Of_Set_Bits_In(register_list) * 4)
then
if ConditionPassed(cond) then
address = start_address
for i = 0 to 15
if register_list[i] == 1
Memory[address,4] = Ri
address = address + 4
assert end_address == address - 4
when you use the proper pairs ib and da (increment before and decrement after) or ia and db with the same register list it is basically the stack push and pop (push and pop are psuedo code for stmdb and ldmia). you started with r1-r3 you did compementary stm/ldm instructions and you got back what you started with, it worked perfectly. As to whether it appears to have done r3 first or r1 first is in the eye of the beholder and the ia/ib/da/db being used on the stm.
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