cortex execute from RAM

I need execute firmware in RAM on a Cortex-M1 processor to erase and rewrite flash. I am using eclipse and launchpad's toolchain. There is a similar question for MDK-ARM: How do I execute a function from RAM on a Cortex-M3 (STM32)?

To run firmware from flash I configure linker script:

MEMORY
{
    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 8K
    RAM (rw)   : ORIGIN = 0x20004000, LENGTH = 16K
}

Then using JLink.exe utility I get:

J-Link>r
Reset delay: 0 ms
Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
J-Link>mem32 0x00,2
00000000 = 20008000 00000101
J-Link>SetPC 0x0101
Info: Cortex-M: Debugger tries to set PC to odd value. Corrected register value from 0x00000101 to 0x00000100
J-Link>wreg MSP 0x20008000
MSP = 0x20008000
J-Link>halt
PC = 00000100, CycleCnt = 00000000
R0 = 00000300, R1 = 00000300, R2 = 00000010, R3 = 400A8000
R4 = 00001000, R5 = 2010108C, R6 = 00002040, R7 = 00000021
R8 = 00000000, R9 = 00000000, R10= 00000008, R11= 00000000
R12= 00000000
SP(R13)= 20008000, MSP= 20008000, PSP= 00000000, R14(LR) = FFFFFFFF
XPSR = 01000000: APSR = nzcvq, EPSR = 01000000, IPSR = 000 (NoException)
CFBP = 00000000, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 00
J-Link>s
00000100:  09 49              LDR     R1, [PC, #+0x24]
J-Link>s
00000102:  0A 4A              LDR     R2, [PC, #+0x28]
J-Link>s
00000104:  0A 4B              LDR     R3, [PC, #+0x28]
J-Link>s
00000106:  00 F0 07 F8        BL      #+0x0E
J-Link>s
00000118:  9B 1A              SUB     R3, R3, R2
J-Link>

Then I want to run firmware from RAM. For that I configure linker script:

MEMORY
{
    FLASH (rx) : ORIGIN = 0x20001000, LENGTH = 8K
    RAM (rw)   : ORIGIN = 0x20004000, LENGTH = 16K
}

And here is I get error while executing that:

 J-Link>r
Reset delay: 0 ms
Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
J-Link>loadbin milandr-template.bin 0x20001000
Downloading file [milandr-template.bin]...O.K.
J-Link>mem32 0x20001000,2
20001000 = 20008000 20001101
J-Link>SetPC 0x20001101
Info: Cortex-M: Debugger tries to set PC to odd value. Corrected register value from 0x20001101 to 0x20001100
J-Link>wreg MSP 0x20008000
MSP = 0x20008000
J-Link>halt
PC = 20001100, CycleCnt = 00000000
R0 = 00000300, R1 = 00000300, R2 = 00000010, R3 = 400A8000
R4 = 00000648, R5 = 00000001, R6 = 00000648, R7 = 00000064
R8 = 00000800, R9 = 00000000, R10= 01000008, R11= 00000000
R12= 00000000
SP(R13)= 20008000, MSP= 20008000, PSP= 00000000, R14(LR) = FFFFFFFF
XPSR = 01000000: APSR = nzcvq, EPSR = 01000000, IPSR = 000 (NoException)
CFBP = 00000000, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 00
J-Link>s
20001100:  09 49              LDR     R1, [PC, #+0x24]
J-Link>s
00000140:  FE E7              B       #-0x04
J-Link>

here is processor jump to address that located in flash area - 0x00000140. Not to at 0x20000102 as expected. Hex files of both cases are similar one in one. It looks like I need to check what difference of results executing of first instructions:

00000100:  09 49              LDR     R1, [PC, #+0x24]

maybe somebody already faced it, and tell an error.

The LDR instruction generates a fault while executing from RAM. Most default fault handlers look like this:

B .

You need to look at the fault registers for more information. But since your original RAM seem to start at 0x20004000, there might be no RAM at address 0x20001000.

You can try a linker file like this:

MEMORY
{
    FLASH (rx) : ORIGIN = 0x20004000, LENGTH = 8K
    RAM (rw)   : ORIGIN = 0x20006000, LENGTH = 8K
}