point of IT instruction ARM assembly

11

I've got the following ARM assembly code.

CMP             R0, #0
ITT EQ
MOVEQ           R0, #0x7FFFFFFF
BXEQ            LR

Firstly, why is the EQ needed after the MOV and BX instructions? The ARM reference says that the condition (EQ) after the ITT will be applied to the first instruction (MOV) in the IT block and then because of the second T in ITT the EQ will be applied to the second instruction (BX) in the IT block. So if the ITT is applying the EQ, why is the EQ needed in MOVEQ and BXEQ?

Secondly, why is the IT instruction needed at all? Why not just have:

CMP             R0, #0
MOVEQ           R0, #0x7FFFFFFF
BXEQ            LR

It's MOV not MOVS so the flags won't be updated and the EQ in BXEQ will still be "referring" to the flag values set by the CMP.

assembly
arm
asked on Stack Overflow Jan 2, 2014 by Jonathan.

3 Answers

13

Why dont you just try it?

.cpu cortex-m3
.thumb
.syntax unified

    CMP             R0, #0
    ITT EQ
    MOVEQ           R0, #0x7FFFFFFF
    BXEQ            LR


    CMP             R0, #0
    MOVEQ           R0, #0x7FFFFFFF
    BXEQ            LR

first try

arm-none-eabi-as vectors.s -o vectors.o
vectors.s: Assembler messages:
vectors.s:13: Error: thumb conditional instruction should be in IT block -- `moveq R0,#0x7FFFFFFF'
vectors.s:14: Error: thumb conditional instruction should be in IT block -- `bxeq LR'
make: *** [vectors.o] Error 1

Which is obvious because there are no conditional versions of those instructions in thumb mode.

so that leaves:

.cpu cortex-m3
.thumb
.syntax unified

    CMP             R0, #0
    ITT EQ
    MOVEQ           R0, #0x7FFFFFFF
    BXEQ            LR

which the tools are happy with

   0:   2800        cmp r0, #0
   2:   bf04        itt eq
   4:   f06f 4000   mvneq.w r0, #2147483648 ; 0x80000000
   8:   4770        bxeq    lr

so we try without the eq

.cpu cortex-m3
.thumb
.syntax unified

    CMP             R0, #0
    ITT EQ
    MOV           R0, #0x7FFFFFFF
    BX            LR

not happy

vectors.s:8: Error: instruction not allowed in IT block -- `mov R0,#0x7FFFFFFF'
vectors.s:9: Error: incorrect condition in IT block -- `bx LR'

I think it must be just a syntax thing to help you out and make sure that you get what you really wanted.

.cpu cortex-m3
.thumb
.syntax unified

    CMP             R0, #0
    IT EQ
    MOVEQ           R0, #0x7FFFFFFF
    BX            LR

gives

   0:   2800        cmp r0, #0
   2:   bf08        it  eq
   4:   f06f 4000   mvneq.w r0, #2147483648 ; 0x80000000
   8:   4770        bx  lr

Notice the bx lr is the same instruction 0x4770, the eq on the end or not on the end seems clearly there as an assembler syntax thing to help you out and make sure you get the right number of instructions tied to the If Then instruction. (which you can see did change between having one conditional instruction and two conditional instructions).

I do find it bothersome

.cpu cortex-m3
.thumb
.syntax unified

    CMP             R0, #0
    IT EQ
    MOVSEQ           R0, #0x7
    BX            LR

    movs r0,#7
    mov r0,#7
    movs.w r0,#7

that in this case the thumb2 extension is used

00000000 <.text>:
   0:   2800        cmp r0, #0
   2:   bf08        it  eq
   4:   f05f 0007   movseq.w    r0, #7
   8:   4770        bx  lr
   a:   2007        movs    r0, #7
   c:   f04f 0007   mov.w   r0, #7
  10:   f05f 0007   movs.w  r0, #7

that is a curiosity.

The reason it is needed at all is obvious from the instruction set documentation. Full blown arm instructions have a 4 bit conditional field on every instruction. thumb instructions do not. At first you simply did the traditional branch on condition to avoid instructions, thumb didnt offer the ARM feature of every instruction being conditional and not needing to flush the pipe. So according to the docs they added the If Then (IT) instruction with ARMv7-M, and as stated in those docs this allows you to make up to four instructions following the if then to become conditional. The above syntax game I believe (have no proof other than it just appears to be so) is there to help on the human error.

Now if not in thumb mode then you absolutely can just apply the conditional to the instruction

.syntax unified

    CMP             R0, #0
    MOVSEQ           R0, #0x7
    BXEQ            LR

    movs r0,#7
    mov r0,#7

gives

00000000 <.text>:
   0:   e3500000    cmp r0, #0
   4:   03b00007    movseq  r0, #7
   8:   012fff1e    bxeq    lr
   c:   e3b00007    movs    r0, #7
  10:   e3a00007    mov r0, #7

and maybe this is the root of your question, but it is very possible that the assembler could just insert the IT instruction for you, but assembly language has a desire to be one to one (despite all the pseudo instructions for all the processors that are out there) so I guess they expect you to explicitly show you want that If Then instruction there and/or that you are going to have an If Then instruction there. The assembler is also helping you by saying you need to use an IT block rather than simply saying it is an invalid instruction.

One further experiment

.cpu arm7t
.thumb
.syntax unified

    CMP             R0, #0
    MOVSEQ           R0, #0x7
    BX            LR

    movs r0,#7

Is bothersome because if you leave the IT in there it knows that is wrong:

vectors.s:7: Error: selected processor does not support Thumb mode `it EQ'

but then in the same breath it says

vectors.s:7: Error: thumb conditional instruction should be in IT block -- `movseq R0,#0x7'
answered on Stack Overflow Jan 2, 2014 by old_timer • edited Jan 2, 2014 by old_timer
9

The ARMv7-A and ARMv7-M edition of the ARM Architecture Reference (A4.2.1 "Conditional instructions) says this:

Although other Thumb instructions are unconditional, all instructions that are made conditional by an IT instruction must be written with a condition. These conditions must match the conditions imposed by the IT instruction. For example, an ITTEE EQ instruction imposes the EQ condition on the first two following instructions, and the NE condition on the next two. Those four instructions must be written with EQ, EQ, NE and NE conditions respectively.

I agree with dwelch that it's likely specified this way to help reduce programming errors, as the condition code isn't encoded in the machine opcode.

Also, for the purpose of the 'unified assembler language' (where the same assembly mnemonics can be used for either 32-bit ARM or Thumb modes), the opposite is done in ARM mode. The IT instructions are checked for consistency with the conditional instructions that follow even though there is no machine opcode generated for the IT instruction:

For maximum portability of UAL assembly language between the ARM and Thumb instruction sets, ARM recommends that:

  • IT instructions are written before conditional instructions in the correct way for the Thumb instruction set.

  • When assembling to the ARM instruction set, assemblers check that any IT instructions are correct, but do not generate any code for them.

answered on Stack Overflow Jan 3, 2014 by Michael Burr • edited Jan 5, 2017 by Osaid
2

You need the IT instruction in thumb mode, where condition bits are not available in the instructions otherwise. Your first example is most probably thumb code and not ARM mode.

why is the EQ needed in MOVEQ and BXEQ?

You can use the inverse condition in an IT block. I think it is also easier to read this way.

answered on Stack Overflow Jan 2, 2014 by Turbo J • edited Jan 2, 2014 by Turbo J

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