Porting a simple MIPS32 program to MIPS64

I am having some difficulty porting the following MIPS32 assembly program to a 64-bit equivalent.

The main issue that I am facing is the following line:

bgtz $s2, loop ; Branch from "loop" on "$s2" greater than zero.

I am not sure why this line causes an error? The instruction should be in MIPS64.

MIPS32

# Description of Program: Computes first 25 Fibonacci numbers and store in an array.

# Description of Register Usage:
#   $s0 = Memory address
#   $s1 = Array Size
#   $s2 = Counter
#   $s3 = F[n] initialized at 1
#   $s4 = F[n - 1]
#   $s5 = F[n - 2]

    .data   ## DECLARATIONS ##
size:   .word   25  # Size of the array or limit.
array:  .word   0 : 25  # Create an array of words to store the 1st 25 Fibonacci numbers.

    .text   ## CODE SECTION ##
main:       la $s1, size    # Load address of size variable.
    la      $s0, array      # Load address of the array.
    lw      $s1, 0($s1)     # Load size of the array.
    addi    $s2, $s1, -2    # [Counter = Array Size - 2] Counter for loop.
    li      $s3, 1          # 1 is the 2nd value of the Fibonacci Sequence.
    sw      $zero, 0($s0)   # F[0] = 0; Store 1st value. 
    sw      $s3, 4($s0)     # F[1] = 1; Store 2nd value.

loop:       lw  $s4, 0($s0) # Get F[0] from memory and assign it to F[n - 2].
    lw      $s5, 4($s0)     # Get F[1] from memory and assign it to F[n - 1].
    add     $s3, $s4, $s5   # F[n] = F[n - 1] + F[n - 2].
    sw      $s3, 8($s0)     # Store the new F[n] into memory at the next availible location.
    addi    $s0, $s0, 4     # Start memory address at the new F[n].
    addi    $s2, $s2, -1    # [Counter = Counter - 1] Counter is initialized at 23.
    bgtz    $s2, loop       # Loop until the counter finally reaches zero. 
exit:       li   $v0, 10    # System call for exit.
    syscall                 # Exit...

###################### MEMORY DUMP ########################
# 0x10010000  0x00000019 0x00000000 0x00000001 0x00000001 #
# 0x10010010  0x00000002 0x00000003 0x00000005 0x00000008 #
# 0x10010020  0x0000000d 0x00000015 0x00000022 0x00000037 #
# 0x10010030  0x00000059 0x00000090 0x000000e9 0x00000179 #
# 0x10010040  0x00000262 0x000003db 0x0000063d 0x00000a18 #
# 0x10010050  0x00001055 0x00001a6d 0x00002ac2 0x0000452f #
# 0x10010060  0x00006ff1 0x0000b520 0x00000000 0x00000000 #
# 0x10010070  0x00000000 0x00000000 0x00000000 0x00000000 #  
###########################################################

MIPS64

      .data ;; DECLARATIONS
size:  .word 25 ; Size of the array or limit.
array: .space 100 ; Create an array of words to store the 1st 25 Fibonacci numbers.

      .text ;; CODE SECTION
main: ori  $s1, $zero, size  ; Load address of size variable.
      ori  $s0, $zero, array ; Load address of the array.
      lw   $s1, 0($s1)       ; Load size of the array.
      addi $s2, $s1, -2      ; [Counter = Array Size - 2] Counter for loop.
      ori  $s3, $zero, 1     ; 1 is the 2nd value of the Fibonacci Sequence.
      sw   $zero, 0($s0)     ; F[0] = 0; Store 1st value. 
      sw   $s3, 4($s0)       ; F[1] = 1; Store 2nd value.

loop: lw   $s4, 0($s0)       ; Get F[0] from memory and assign it to F[n - 2].
      lw   $s5, 4($s0)       ; Get F[1] from memory and assign it to F[n - 1].
      add  $s3, $s4, $s5     ; F[n] = F[n - 1] + F[n - 2].
      sw   $s3, 8($s0)       ; Store the new F[n] into memory at the next available location.
      addi $s0, $s0, 4      ; Start memory address at the new F[n].
      addi $s2, $s2, -1     ; [Counter = Counter - 1] Counter is initialized at 23.
      bgtz $s2, loop        ; Loop until the counter finally reaches zero. 
exit: halt                  ; Exit...

In MIPS assembly, you may need to provide a valid instruction for the BDS (branch delay slot) and following BDS. These will be the 2 instructions after bgtz. The BDS is executed nevertheless, whether the branch is taken or not. The post-branch is executed only if branch is not taken.

For the program to be valid, you need to provide a proper instruction after the branch (BDS) and following.

In the MIPS32 listing above you have a load-immediate li $v0, 10 as BDS, and a syscall as post-branch. But in MIPS64 case, you don't have a valid BDS slot instruction and Post-branch instruction.

We see this on OCTEON (MIPS64) CPUs as well, when doing detailed performance tuning at instruction level.

Just put in a nop in BDS , and the assembly will be fine.