cpuid instruction on i5-2500k: MMX, SSE, SSE2 bits are not set

Is this expected? I expected my Sandy Bridge CPU to report that it can handle MMX, SSE, and SSE2 instructions. Are these bits not set because these "old" instruction sets have been "superceded" by some of the newer ones?

I used this code here to put CPU detection into my code.

#include "CPUID.h"
int main(int argc, char *argv[]) {
    CPUID cpuid;
    cpuid.load(0);
    printf("CPU: %.4s%.4s%.4s", 
        (const char*)&cpuid.EBX(),
        (const char*)&cpuid.EDX(),
        (const char*)&cpuid.ECX()
    );
    char brand[0x30];
    cpuid.load(0x80000002); memcpy(brand,&cpuid.EAX(),16);
    cpuid.load(0x80000003); memcpy(brand+16,&cpuid.EAX(),16);
    cpuid.load(0x80000004); memcpy(brand+32,&cpuid.EAX(),16);
    printf("%.48s\n",brand);
    cpuid.load(1);
    // tests bit 23 of ECX for popcnt instruction support
    printf("MMX - %s\n", cpuid.EAX() & (1 << 23) ? "yes" : "no");
    printf("SSE - %s\n", cpuid.EAX() & (1 << 25) ? "yes" : "no"); 
    printf("SSE2 - %s\n", cpuid.EAX() & (1 << 26) ? "yes" : "no"); 
    printf("SSE3 - %s\n", cpuid.ECX() & (1 << 0) ? "yes" : "no"); 
    printf("SSSE3 - %s\n", cpuid.ECX() & (1 << 9) ? "yes" : "no"); 
    printf("SSE4.1 - %s\n", cpuid.ECX() & (1 << 19) ? "yes" : "no"); 
    printf("SSE4.2 - %s\n", cpuid.ECX() & (1 << 20) ? "yes" : "no"); 
    printf("AES - %s\n", cpuid.ECX() & (1 << 25) ? "yes" : "no"); 
    printf("AVX - %s\n", cpuid.ECX() & (1 << 28) ? "yes" : "no"); 
    printf("HT - %s\n", cpuid.EAX() & (1 << 28) ? "yes" : "no"); 
    printf("IA64 (emulating x86) - %s\n", cpuid.EAX() & (1 << 30) ? "yes" : "no"); 
    printf("Hypervisor? - %s\n", cpuid.ECX() & (1 << 31) ? "yes" : "no"); 
    printf("popcnt - %s\n", cpuid.ECX() & (1 << 23) ? "yes" : "no");
    return 0;
}

output:

CPU: GenuineIntel       Intel(R) Core(TM) i5-2500K CPU @ 3.30GHz
MMX - no
SSE - no
SSE2 - no
SSE3 - yes
SSSE3 - yes
SSE4.1 - yes
SSE4.2 - yes
AES - yes
AVX - yes
HT - no
IA64 (emulating x86) - no
Hypervisor? - no
popcnt - yes

Dumb mistake. I assumed the first row in the table was for EAX but it's for EDX.

Correct results are produced. Well, HT isn't supported by this chip but maybe that one's always set.

Update: turns out the "HT" means >1 logical thread on package (of which this chip has 4).

CPU: GenuineIntel       Intel(R) Core(TM) i5-2500K CPU @ 3.30GHz
MMX - yes
SSE - yes
SSE2 - yes
SSE3 - yes
SSSE3 - yes
SSE4.1 - yes
SSE4.2 - yes
AES - yes
AVX - yes
HT - yes
IA64 (emulating x86) - no
Hypervisor? - no
popcnt - yes